Unwanted offset voltage may be introduced into electronic devices during operation, for which compensation is desired to assure proper functionality of the electronic devices and/or the systems incorporating such devices. For example, a high speed digital-to-analog converter (DAC) may include multiple unit switching elements (unit DACs) to respectively provide analog conversion of portions of data (bits) in input parallel data streams. Timing skew in the unit switching elements of the high speed DAC may degrade the spurious or noise floor performance. Attempts to keep the timing skew low enough for reliable operation include employment of a number of conventional techniques.
For example, an electrical device or system may be carefully laid out to avoid systematic mismatch between the parallel paths. This is usually not sufficient on its own because of random mismatch. Using large devices and minimizing signal delay in the parallel paths typically reduce random mismatch, which may be quite effective. However, reducing mismatch in this manner results in higher power dissipation, and may also reduce analog bandwidth if the device is too large. Dynamic element matching (DEM) techniques may spread high-order spurs caused by timing skews into noise, improving spurious-free dynamic range (SFDR) at the cost of degrading the noise floor. However, improvement in regard to low-order spurs (e.g., second and third order spurs) is typically limited. Also, if the noise floor degradation is unacceptable, then the timing skews must be corrected, as opposed to simply randomized into noise.
Another example involves resampling data currents with a single low-skew clock. This may be effective at lower sample rates where data transitions are fully blocked by the resampler. However, at very high sample rates, resampler operation becomes sloppy and some of the data transition errors leak through. Also, another conventional technique involves inserting a programmable delay into the clock path of each parallel path in the switching DAC to enable calibration. Although this technique has potential for good performance, adding a programmable delay into each parallel data slice with adequate range and precision significantly complicates the layout. Depending on how the programmable delay is implemented, it may increase uncalibrated mismatch, degrading uncalibrated performance. The calibration procedure typically requires a spectrum analyzer, so in-system recalibration is expensive and time consuming.
Thus, what is needed is a simple and reliable system and technique that compensates for offset voltage.